1. Field of the Invention
The present invention relates to a semiconductor memory device. More particularly, it relates to a layout configuration of n-MOS memory cells, each being constituted using n-channel MOS transistors, which are arranged in the form of a matrix in a semiconductor memory device.
2. Description of the Related Art
Generally, in a semiconductor memory device, a plurality of memory cells are arranged in a matrix along row and column directions on a chip. In the arrangement form, each memory cell typically includes a flip-flop having two sets of driver transistors and load elements which are cross-coupled, and a pair of transfer gate transistors connected between a pair of data retaining nodes of the flip-flop and a pair of complementary bit lines, respectively. Also, regions of power supply lines for feeding power to the respective memory cells are incorporated into the above arrangement, together with regions of the memory cells.
In such a layout configuration, for example, where a further power supply line is arranged in the matrix of memory cells, a problem may be posed. Namely, since a layout pattern for the power supply line generally has no common portion with respect to a layout pattern of the memory cells, it is necessary to take the trouble to make or devise the layout pattern for the power supply line. This work is troublesome.
Also, depending on the arrangement form of each memory cell or the communization form of contact windows between each source/drain of the driver transistors or the transfer gate transistors and the power supply line or the bit lines, a problem occurs in that the entire chip area is increased by a wiring region corresponding to the power supply line.
To prevent an increase in the chip area, for example, an approach to reduce a distance between patterns of the complementary bit lines can be proposed. However, where the distance between the bit lines is simply reduced, respective regions (gate, source, drain) constituting each transistor may be changed in shape, depending on the arrangement form of the memory cells or the communization form of the contact windows. In this case, the gate width or the gate length of each transistor is changed and thus the characteristics thereof are also changed. This leads to a lowering in the operation reliability.
Note, the problems in the prior art will be explained later in detail in contrast with the preferred embodiments of the present invention.